“Complementary metal oxide semiconductor” (CMOS) is an example of a technology for use in integrated circuits (or ICs) which uses metal oxide semiconductor field effect transistors (MOSFETS). These may be either n-type channel MOSFETS (NMOS transistors) or p-type channel MOSFETS (PMOS transistors).
In a synchronous digital sub-system within a circuit such as a CMOS integrated circuit, it is frequently necessary to receive messages that have asynchronous timing with respect to the part of the sub-system that must receive the message. Such asynchronous messages may have been sent from other synchronous sub-systems which have relatively asynchronous clocks with respect to the receiving subsystem, or may arrive from some external source.
To determine whether the arriving asynchronous digital signal is logically a ‘zero’ or a ‘one’, the synchronous receiving circuit includes a latch circuit that samples the incoming signal when a local clock signal transitions. When the latch has sampled, its output should reflect the state of the received signal when the clock transitioned.
However, if the incoming signal is in the process of changing between the two binary states when the clock transition occurs, then it can take a relatively long time before the latch output settles to a voltage that represents one of the two binary states to any subsequent logic gate. This phenomenon is known as metastability.
This can be particularly problematic in any situation where the sampled signal is used directly or indirectly to update more than a single bit of state within the receiving circuit. In this case, the updated state bit values may themselves be metastable or may imply conflicting decisions about the state of the sampled signal. Thus, the digital receiver circuit can fail to behave like the digital state machine model from which it was derived and thus will fail to function correctly.
The situation is illustrated schematically in FIG. 1, which shows a digital logic circuit including two internally synchronous subsystems 10 and 20 that are relatively asynchronous with respect to one another. The first subsystem includes a first clock 12 (Ck1) arranged to generate a first clock signal, along with components connected to be clocked by the first clock signal including a transmitting component 14 (Tx), thus forming a first clock domain. The second subsystem 20 includes a second clock 22 (Ck2) arranged to generate a second clock signal, along with components connected to be clocked by the second clock signal including a latch 24 and one or more receiving components 26a and 26b (Rx), thus forming a second clock domain. The output of the transmitting component 14 in the first subsystem 14 is connected to the input of the latch 24 in the second subsystem 20, and the output of the latch 24 is coupled to inputs of the receiving components 26a and 26b in the second subsystem 20. The transmitting component 14 sends a logic signal from the first subsystem 10 to the second subsystem 20, timed according to the first clock signal. The latch 24 receives this logic signal at its input, but only adopts the signal's logical value at its output on a tick of the second clock signal, thus synchronizing the timing of the received logic signal to the second clock signal. However, if the clock ticks while the received logic signal is in transition between two logical levels, from one to zero or vice versa, then as discussed the resulting metastability can be slow to resolve and thus may lead to errors. For example, the two receiving components 26a and 26b may detect different logical values.
To minimize the likelihood of such problems, it is important that the output of the sampling latch circuit (e.g., 24) resolves quickly enough to a value representing an unambiguous digital zero or one with an extremely low probability of failure.
Traditionally, a clocked CMOS feedback latch circuit has been used for this task. When the clock is in one state, the latch is said to be “transparent” reflecting the input state at the output terminal. When the clock transitions to the other state, the input becomes irrelevant, the latch is said to be “closed” and an internal feedback circuit is turned on. It is this positive feedback loop that resolves a meta-stable output voltage to a value representing an unambiguous digital state.
A typical example is illustrated schematically in FIG. 2. This commonly used CMOS latch circuit is ‘transparent’ (output Q becomes equal to input D) while the clock input CK=Vss=0V (logic 0) and ‘closed’ when CK=Vdd (logic 1). When the latch is closed, MOS transistors n1 and p1 are off while transistors n3 and p3 are on. This closes the feedback loop consisting of the inverter i1 and the tri-state gate including transistors n3, n4, p3 and p4.
The speed with which this feedback loop can resolve a metastable value depends on many factors—one of them being the power supply voltage (Vdd).
If the feedback loop is included of two inverting CMOS logic gates (for example CMOS inverters, transmission gates, tri-state drivers) connected back-to-back then the speed of metastability resolution degrades very rapidly when the supply voltage becomes less than two times the MOS device threshold voltage (Vthreshold). This is because when the circuit is in the metastable state, both of the logic gates' inputs are at approximately half the supply voltage (Vdd). If Vdd<2Vthreshold, this means that the MOS devices have a gate-source voltage Vgs≈Vdd/2<Vthreshold, meaning that they are in or near to the sub-threshold region of operation and conducting very little current indeed; making the voltage change necessary to resolve the metastable state extremely slow initially.
CMOS logic continues to work relatively fast at Vdd=2Vthreshold, slowing down dramatically as Vdd approaches Vthreshold.
There is a strong incentive to minimize the power consumption of integrated circuits for mobile (battery powered) applications by setting Vdd to the minimum value at which the circuits are still functional.
If part of their functionality includes resolving metastability, then there is a danger that the metastability resolving latch circuits will limit the level to which Vdd can be reduced rather than the speed of the CMOS logic; potentially making power consumption higher than otherwise necessary in a low-speed mode of operation.
Special, low Vthreshold devices can be used in the resolving latch circuit to enhance performance at low supply voltages. However, it costs more to manufacture integrated circuits that include such devices. If the resolvers are the only circuits in the integrated circuit that require such special devices, then this solution can make the IC more costly.
Some synchronizing (i.e., metastability resolving) latch circuits have been disclosed. They fall into two groups.
Firstly there are enhanced versions of the circuit illustrated in FIG. 2 (two back-to-back CMOS gates). Examples are:
U.S. Pat. No. 4,617,480—“High speed data synchronizer which minimizes circuitry”
U.S. Pat. No. 4,469,964—“Synchronizer circuit”
U.S. Pat. No. 4,544,851—“Synchronizer circuit with dual input”
U.S. Pat. No. 6,512,406—“Backgate biased synchronizing latch”
U.S. Pat. No. 6,072,346—“Metastable protected latch”
However, all of these are still subject to the performance limitations at low operating voltages, as described above.
Secondly, there are ideas based on the false premise that any immediate binary decision can be made either implicitly or explicitly based on a meta-stable value (including detecting whether the value is or is not meta-stable). Examples are:
U.S. Pat. No. 5,034,967—“Metastable-free digital synchronizer with low phase error”
U.S. Pat. No. 6,771,099—“Synchronizer with zero metastability”
U.S. Pat. No. 6,531,905—“Flip-flop with metastability reduction”
U.S. Pat. No. 4,999,528—“Metastable-proof flip-flop”